1. Field of the Invention
The present invention relates to a timing control circuit for a semiconductor memory device and, more particularly, to a circuit capable of controlling timing before and after package by using a fuse.
2. Description of the Related Art
As shown in FIG. 1, a delay set using metal mask has been employed to control signal timing in a semiconductor device. FIG. 1 is an exemplary circuit diagram of a circuit generating a signal delay necessary for active and precharge modes according to the level of signal A applied to input terminal.
The conventional timing control circuit comprises: a delay unit 10 including a plurality of delay means, for example, a first delay means 11 and a second delay means 13 connected in a row; a metal switching means 20 formed by using a metal mask in a semiconductor process to determine whether the second delay means 13 is employed or not; and a signal transmission unit 30 for receiving signal controlled by the delay unit 10 and the metal switching means 20 and then, outputting a timing controlled signal.
The signal transmission unit 30 comprises: a NAND gate NAND for receiving signal according to the connected state of the second delay means 13 and the metal switching means 20; a first inverter INV1 for inverting signal from the NAND gate; a first NOR gate NOR1 for receiving signal from the first delay means 11 and the first inverter INV1; a second inverter INV2 for inverting signal from the first NOR gate NOR1; and a second NOR gate NOR2 for receiving the externally-inputted signal and signal from the second inverter INV and then, outputting timing controlled signal of the externally-inputted signal by each delay means. The metal switching means 20 operates as a switching to connect the second delay means 13 with the first NAND gate NAND 1 or the first NAND gate NAND 1 with ground. That is, when the metal switching means 20 is connected with ground, timing of externally-inputted signal is controlled only by the first delay means 11 and when the metal switching means 20 connects the second delay means 13 with the first NAND gate NAND 1, timing of externally-inputted signal is controlled by the first and the second delay means 11, 13.
However, conventional timing control circuit using the metal switching means 13 has a problem that delay time is increased or reduced by process variables after manufacturing and packaging products. And, it is difficult to solve problems generated by undesirable timing, for example, problems generated on the ground that tRCD, tRP or other timing spec. is not satisfied.
Therefore, the present invention has been made to solve the above-mentioned problems and a primary objective of the present invention is to provide a timing control circuit for semiconductor device satisfying timing specification by enabling timing of internal signal to be controlled after packaging the semiconductor device.
In order to accomplish the above objective, a timing circuit of the present invention includes a signal delay unit comprising delay elements and for delaying externally-received signal for a predetermined time and then, outputting the result and a fuse unit capable of determining whether to enable or disable semiconductor device after packaging, and determining whether to delay signal or not by the delay element according to whether it is enabled or disabled, thereby controlling delay time of signal by the signal delay unit.
The fuse unit desirably comprises electrical fuse circuit blowing through current. And, the electrical fuse circuit includes a fuse comprising: a first node; a MOS transistor wherein source voltage VDD is applied to on channel terminal, a signal for fuse program is applied to gate, and other channel terminal is connected with the first node; a fuse wherein one end is connected with the first node and other end is applied with a predetermined level of control voltage VSB; and resistor wherein one end is connected with the first node and other end is applied with source voltage VDD.
More desirably, the electrical fuse circuit further includes a first inverter whose input terminal is connected with other channel terminal of the MOS transistor; and a second inverter whose input terminal is connected with output terminal of the first inverter, the output signal determining whether to delay signal by the delay element or not. And, more desirably, the electrical fuse circuit further includes a latch unit whose input terminal is connected to output terminal of the second inverter and the source voltage VDD is applied as the control voltage VSB after level of the first node is latched to the latch unit.
The fuse unit comprises two or more electrical fuse circuits, wherein at least one of them is employed to reduce signal delay time by the signal delay unit and at least one of them to increase signal delay time by the signal delay unit.
According to timing control circuit of the present invention, it is possible to control timing of internal signal after packaging semiconductor device, thereby satisfying timing specification. Therefore, the present invention is effective in improving productivity and quality in spite of process variables.